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visit our website: www.e2v.com for the latest version of the datasheet e2v semiconductors sas 2007 ts68882 cmos enhanced floating-point co-processor datasheet 0852b?hirel?06/07 features eight general-purpose floating-point data registers, each supporting a full 80-bit extended precision real data format (a 64-bit mantissa plus a sign bit, and a 15-bit signed exponent) a 67-bit arithmetic unit to allow very fast calculations wit h intermediate are precision greate r than the extended precision format a 67-bit barrel shifter for high-speed shi fting operations (for normalizing etc.) special-purpose hardware for high-speed conversion between single, double, an d extended formats and the internal extended format an independent state machine to co ntrol main processor communication for pipelined instruction processing forty-six instructions, includ ing 35 arithmetic operations full conformation to the ieee ? 754 standard, including all requirements and suggestions support of functions not defined by the ieee standard, including a full set of trigonometric and transcendental functions seven data type types: byte, word and long integers; single, double, and extend ed precision real nu mbers; and packed binary coded decimal string real numbers twenty-two constants available in the on-chip rom, including , e, and powers of 10 virtual memory/machine operations efficient mechanisms for pro cedure calls, context switch es, and interrupt handling fully concurrent instruction ex ecution with the main processor fully concurrent instruction execution of multiple floating-point instructions use with any host processor, on an 8-, 16- or 32-bit data bus available in 16.67, 20, 25 and 33 mhz for t c from -55c to +125c v cc = 5v 10% description the ts68882 enhanced floating-point co-processor is a full impl ementation of the ieee standard for binary floating-point arithmetic (754) for use with the thomson ts68000 family of microprocessors. it is a pin and software compatible upgrade of the ts68881 with optimized mpu interface that provides over 1.5 times the performance of the ts68881. it is implemented using vlsi technology to give systems designer s the highest possible functionality in a physically small device. intended primarily for use as a co-processor to the ts68020/68030 32-bit microprocessor units (mpus), the ts68882 pro- vides a logical extension to the main mp u integer data processing ca pabilities. it does this by providing a very high performance floating-point arithmetic unit and a set of floa ting-point data register s that are utilized in a manner that is ana l- ogous to the use of the integer data registers. the ts68882 instruction set is a natural extension of all earlier members of the ts68000 family, and supports all of the addressing modes of the host mpu. due to the flexible bus interface of the ts68000 family, the ts68882 can be used with any of the mp u devices of the ts68000 family, and it may also be used as a peripheral to non-ts68000 processors.
2 0852b?hirel?06/07 ts68882 e2v semiconductors sas 2007 screening/quality this product could be manufactured in full compliance with either: mil-std-883 class b desc 5962-89436 or according to e2v-grenoble standards 1. introduction the ts68882 is a high-performance floating-point device designed to interface with the ts68020 or ts68030 as a co-processor. this device fully supports the ts68000 virtual machine architecture, and is implemented in hcmos, e2v?s low power, small geometry process. this process allows cmos and hmos (high-density nmos) gates to be combined on the same device. cmos structures are used where speed and low power is required, and hmos structures are used where minimum silicon area is desired. the hcmos technology enables the ts68882 to be very fast while consuming less power than comparable hmos, and still have a reasonably small die size. with some performance degradation, the ts68882 can also be used as a peripheral processor in sys- tems where the ts68020 or ts68030 is not the main processor (i.e., ts68000, ts68010). the configuration of the ts68882 as a peripheral processor or co-processor may be completely transparent to user software (i.e., the same object code may be executed in either configuration). the architecture of the ts68882 appears to the user as a logical extension of the ts68000 family archi- tecture. coupling of the co-processor interface allows the ts68020/ts68030 programmer to view the ts68882 registers as though the registers are resident in the ts68020/ts68030. thus, a ts68020 or ts68030/ts68882 device pair appears to be one proc essor that supports seven floating-point and inte- ger data types, and has eight integer data registers, eight address registers, and eight floating-point data registers. as shown in figure 1-1 , the ts68882 is internally divided into four processing elements; the bus inter- face unit (biu), the conversion control unit (ccu), the execution control unit (ecu), and the microcode control unit (mcu). the biu communicates with the main processor, the ccu controls the main processor communications dialog and performs some data conversions, and the ecu and mcu execute most floating-point calculations. the biu contains the co-processor interface registers, and the 32-bit control, and instruction address registers. in addition to these registers, the register select and dsack timing control logic is contained in the biu. finally, the status flags used to monitor t he status of communications with the main processor are contained in the biu. r suffix pga 68 ceramic pin grid array f suffix cqfp 68 ceramic quad flat pack
3 0852b?hirel?06/07 e2v semiconductors sas 2007 ts68882 the ccu contains special-purpose hardware that performs conversions between the single, double, and extended precision memory data formula and the intern al data format used by the ecu. it also contains a state machine that controls communications with the main processor during co-processor interface dialogs. the eight 80-bit floating-point data registers (fp0-fp7) are located in the ecu. in addition to these reg- isters, the ecu contains a high-speed 67-bit arithmetic unit used for both mantissa and exponent calculations, a barrel shifter that can shift from 1-bit to 67-bits in one machine cycle, and rom constants (for use by the internal algorithms or user programs). the mcu contains the clock generator, a two-level microcoded sequencer that controls the ecu, the microcode rom, and se lf-test circuitry. the built-in self-test capabilities of the ts 68882 enhance reliabil- ity and ease manufacturing requirements; however, these diagnostic functions are not available to the user.
4 0852b?hirel?06/07 ts68882 e2v semiconductors sas 2007 figure 1-1. ts68882 simplified block
5 0852b?hirel?06/07 e2v semiconductors sas 2007 ts68882 2. pin assignments figure 2-1. pga terminal designation * reserved for future atmel-grenoble use
6 0852b?hirel?06/07 ts68882 e2v semiconductors sas 2007 figure 2-2. cqfp terminal designation 2.1 functional signal descriptions this section contains a brief description of the input and output signals for the ts68882 floating-point co- processor. the signals are functionally organized into groups as shown in figure 2-3 . figure 2-3. ts68882 input/output signals note: the terms assertion and negation are used extensivel y. this is done to avoid confusion when describing ?active-low? and ?active-high? signals. the term assert or assertion is used to indicate that a signal is active or true, independent of whether that level is represented by a high or low voltage. the term negate or nega- tion is used to indicate that a signal is inactive or false.
7 0852b?hirel?06/07 e2v semiconductors sas 2007 ts68882 2.2 signal summary table 2-1 provides a summary of all the ts68882 signals described in this section. 3. detailed specifications 3.1 scope this drawing describes the specific requirem ents for the microprocessor 68882, 16.67, 20 mhz and 25 mhz, in compliance wit h mil-std-883 class b. 3.2 applicable documents 1. mil-std-883: test methods and procedures for electronics 2. mil-prf-38535 appendix a: general specifications for microcircuits 3. desc drawing 5962 - 89436xxx the microcircuits are in accordance with the applicable document and as specified herein. 3.3 design and construction 3.3.1 terminal connections depending on the package, the terminal connections shall be as shown in figure 2-1 on page 5 and fig- ure 2-2 on page 6 . 3.3.2 lead material and finish lead material and finish shall be any option of mil-std-1835. table 2-1. signal summary signal name mnemonic input/outp ut active state three state address bus a0 - a4 input high data bus d0 - d31 input/output high yes size size input low address strobe as input low chip select cs input low read/write r/w input high/low data strobe ds input low data transfer and size acknowledge dsack0 , dsack1 output low yes reset reset input low clock clk input sense device sense input/output low no power input v cc input ground gnd input
8 0852b?hirel?06/07 ts68882 e2v semiconductors sas 2007 3.3.3 package the macrocircuits are packaged in hermetically se aled ceramic packages which are conform to case outlines of mil-std-1835 (when defined): 68-pin sq.pga up pae outline 68-pin ceramic quad flat pack cqfp the precise case outlines are described on figure 11-1 and figure 11-2 . 4. electrical characteristics 4.0.1 recommended condition of use unless otherwise stated, all voltages are referenced to the reference terminal (see table 2-1 ). notes: 1. test load, see figure 7-2 . 2. capacitance is periodically sampled rather than 100% tested. table 4-1. absolute maximum ratings symbol parameter test conditions min max unit v cc supply voltage -0.3 +7.0 v v i input voltage -0.3 +7.0 v p dmax max power dissipation t case = -55c to +125c 0.75 w t case operating temperature m suffix -55 +125 c v suffix -40 +85 c t stg storage temperature -55 +150 c t leads lead temperature max 5 sec. soldering +270 c table 4-2. dc electrical characteristics v cc = 5.0 v dc 10%; gnd = 0 v dc ; tc = -55c to +125c symbol parameter min max unit v cc supply voltage 4.5 5.5 v t case operating temperature -55 +125 c v ih input high voltage 2.0 v cc v v il input low voltage gnd - 0.3 0.8 v i in input leakage current at 5.5v clk , reset , r/w , a0-a4, cs , ds , as, size 10 a i tsi hi-z (off state) input current at 2.4v/0.4v dsack0, dsack1 , d0-d31 20 a v oh output high voltage (ioh = -400 a) (1) dsack0, dsack1 , d0-d31 2.4 v v ol output low voltage (iol = 5.3 ma) (1) dsack0, dsack1 , d0-d31 0.5 v i ol output low current (vol = gnd) sense 500 a p d power dissipation 0.75 w c in capacitance (v in = 0, t a = 25c, f = 1 mhz) (2) 20 pf c l output load capacitance 130 pf
9 0852b?hirel?06/07 e2v semiconductors sas 2007 ts68882 5. thermal characteristics 6. power considerations the average chip-junction temperature, t j, in c can be obtained from: t j = t a + (p d + ja )(1) t a = ambient temperature, c ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i cc x v cc, watts - chip internal power p i/o = power dissipation on input and output pins - user determined for most applications p i/o < p int and can be neglected. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k: (t j + 273) (2) solving equations (1) and (2) for k gives k = p d . (t a + 273) + ja p d 2 (3) where k is constant pertaining to the particular pa rt k can be determined from the equation (3) by mea- suring pd (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . the total thermal resistance of a package ( ja ) can be separated into two components, jc and ca , rep- resenting the barrier to heat flow from the semi conductor junction to the package (case), surface ( jc ) and from the case to the outside ambient ( ca ). these terms are related by the equation: ja = jc + ca (4) ja is device related and cannot be influenced by the user. however, ca is user dependent and can be minimized by such thermal management techniques as heat sinks, ambient air cooling and thermal con- vection. thus, good thermal management on the part of the user can significantly reduce ca so that ja approximately equals jc. substitution of jc for ja in equation (1) will result in a lower semiconductor junction temperature. 6.1 mechanical and environmental the microcircuits shall meet all mechanical environmental requirements of either mil-std-883 for class b devices. table 5-1. package symbol parameter value rating pga 68 ja thermal resistance - ceramic junction to ambient 33 c/w jc thermal resistance - ceramic junction to case 4 c/w cqfp ja thermal resistance - ceramic junction to ambient 33 c/w jc thermal resistance - ceramic junction to case 3 c/w
10 0852b?hirel?06/07 ts68882 e2v semiconductors sas 2007 6.2 marking the document defines the markings th at are identified in the related reference documents. each micro- circuit is legible and permanently marked with the following information as minimum: e2v-grenoble logo manufacturer?s part number class b identification date-code of inspection lot esd identifier if available country of manufacturing 6.3 quality conf ormance inspection 6.3.1 desc/mil-std-883 is in accordance with mil-m-38510 and method 5005 of mil-std-883. group a and b inspections are performed on each production lot. group c and d inspection are performed on a periodical basis. 7. electrical characteristics 7.1 general requirements all static and dynamic electrical characteristics specified and the relevant measurement conditions are given below. for inspection purpose, refer to relevant specification: static electrical characteristic s for all electrical variants. dynamic electrical characteristics for 68882-16 (16.67 mhz), 68882-20 (20 mhz), 68882-25 (25 mhz) and 68882-33 (33 mhz). for static characteristics, test methods refer to clause ?test load? on page 14 hereafter of this specifica- tion (table 5). for dynamic characteristics (tables 6 and 7), test methods refer to iec 748-2 method number, where existing. table 7-1. static characteristics v cc = 5.0 v dc 10%; gnd = 0 v dc ; tc = -55/+125c or -40/+85c symbol parameter min max unit v ih input high voltage 2.0 v cc v v il input low voltage gnd - 0.3 0.8 v i in input leakage current at 5.5v clk, reset , r/w , a0-a4, cs , ds , as , size 10 a i tsi hi-z (off state) input current at 2.4v/0.4v dsack0 , dsack1 , d0-d31 20 a v oh output high voltage (i oh = -400 a) (1) dsack0 , dsack1 , d0-d31 2.4 v v ol output low voltage (i ol = 5.3 ma) (1) dsack0 , dsack1 , d0-d31 0.5 v i ol output low current (v ol = gnd) sense 500 a
11 0852b?hirel?06/07 e2v semiconductors sas 2007 ts68882 notes: 1. test load, see figure 7-2 . 2. capacitance is periodically sampled rather than 100% tested. 7.2 dynamic (switching) characteristics the limits and values given in this section apply over the full case temperature range -55c to +125c and v cc in the range 4.5v to 5.5v, see ?ac electrical specification definitions? on page 14. the numbers (n) refer to the timing diagrams. see figure 7-1 , figure 7-3 , figure 7-4 , figure 7-5 and figure 7-6 . figure 7-1. clock input timing diagram note: timing measurements are referenced to and from a low voltage of 0.8v and a high voltage of 2.0v, unless otherwise noted. the voltage swing through this ran ge should start outside, and pass through, the range such that the rise of fall will be linear between 0.8v and 2.0v. i cc maximum supply current (v cc = 5.5v; clk = f max ; part in reset) 136 ma c in capacitance (v in = 0, t a = 25c, f = 1mhz) (2) 20 pf c l output load capacitance 130 pf table 7-1. static characteristics (continued) v cc = 5.0 v dc 10%; gnd = 0 v dc ; tc = -55/+125c or -40/+85c symbol parameter min max unit table 7-2. ac electrical characteristics - clock input v cc = 5.0 v dc 10%; gnd = 0 v dc; tc = -55c to +125c (see figure 7-1 ) number parameter 16.67 mhz 20 mhz 25 mhz 33.33 mhz unit min max min max min max min max frequency of operation 8 16.67 12.5 20 12.5 25 16.7 33.33 mhz 1 clck time 60 125 50 80 40 80 30 60 ns 2, 3clock pulse width 2495205415591466ns 4, 5 rise and fall times 5 5 4 3 ns
12 0852b?hirel?06/07 ts68882 e2v semiconductors sas 2007 table 7-3. ac electrical characteristics ? read and write cycles (1) v cc = 5.0 v dc 10%; gnd = 0 v dc; tc = -55c/+125c or tc = -40c/+85c (see figure 7-4 on page 16 , figure 7-5 on page 17 , figure 7-6 on page 18 ) n parameter 16.67 mhz 20 mhz 25 mhz 33.33 mhz unit minmaxminmaxminmaxminmax 6 address valid to as asserted (5) 15 10 5 5 ns 6a address valid to ds asserted (read) (5) 15 10 5 5 ns 6b address valid to ds asserted (write) (5) 50 50 35 26 ns 7as negated to address invalid (6) 10 10 5 5 ns 7a ds negated to address invalid (6) 10 10 5 5 ns 8 cs asserted to as asserted or as asserted to cs asserted (9) 0000ns 8a cs asserted to ds asserted or ds asserted to cs asserted (read) (9) 0000ns 8b cs asserted to ds asserted or ds asserted to cs asserted (write) (9) 30 25 20 15 ns 9as negated to cs negated 10 10 5 5 ns 9a ds negated to cs negated 10 10 5 5 ns 10 r/w high to as asserted (read) 15 10 5 5 ns 10a r/w high to ds asserted (read) 15 10 5 5 ns 10b r/w low to ds asserted (write) 35 30 25 25 ns 11 as negated to r/w low (read) or as negated to r/w high (write) 10 10 5 5 ns 11a ds negated to r/w low (read) or ds negated to r/w high (write) 10 10 5 5 ns 12 ds width asserted (write) 40 38 30 23 ns 13 ds width negated 40 38 30 23 ns 13a ds negated to as asserted (4) 30 30 25 18 ns 14 cs , ds asserted to data-out valid (read) (2) 80 45 45 30 ns 15 ds negated to data-out invalid (read) 0 0 0 0 ns 16 ds negated to data-out high impedance (read) 50 35 35 30 ns 17 data-in invalid to ds asserted (write) 15 10 5 5 ns 18 ds negated to data-in invalid (write) 15 10 5 5 ns 19 start true to dsack0 and dsack1 asserted (2) 50 35 25 20 ns 19a dsack0 asserted to dsack1 asserted (skew) (7) -1515-1010-1010 5 ns 20 dsack0 or dsack1 asserted to data-out valid 50 43 32 17 ns
13 0852b?hirel?06/07 e2v semiconductors sas 2007 ts68882 notes: 1. timing measurements are referenced to and from a low vo ltage of 0.8v and a high volta ge of 2.0v, unless otherwise noted . the voltage swing through this range should start outside, and pa ss through, the range such that the rise or fall will be linea r between 0.8v and 2.0v. 2. these specifications onl y apply if the ts68882 has completed all internal operations initiated by the termination of the prev i- ous bus cycle when ds was negated. 3. synchronous read cycles occur only when the save or response cir locations are read. 4. this specification only applies to systems in which back-to-back accesses (read-write or write-write) of the operand cir can occur. when the ts68882 is used as a co-processor to the ts68020/68030, this can occur when the addressing mode is immediate. 5. if the size pin is not strapped to either v cc or gnd, it must have the same setup times as do addresses. 6. if the size pin is not strapped to either v cc or gnd, it must have the same hold times as do addresses. 7. this number is reduced to 5 nanoseconds if dsack0 and dsack1 have equal loads. 8. start is not an external signal; rather, it is the logical conditi on that indicates the start of an access. the logical equation for this condition is start = cs + as + (r/w ds) . 9. if a subsequent access is not a fpcp access, cs must be negated before the assertion of as and/or ds on the non-fpcp access. these specifications replace the old specifications 8 and 8a (the old specificat ions implied that in all cases, transi- tions in cs must not occur simultaneously with transitions of as or ds. this is not a requirement of the ts68882). 21 start false to dsack0 and dsack1 negated (8) 50 30 40 30 ns 22 start false to dsack0 and dsack1 high impedance (8) 70 55 55 40 ns 23 start true to clock high (synchronous read) (3)(8) 0000ns 24 clock low to data-out valid synchronous read) (3) 105 80 60 45 ns 25 start true to data-out valid (synchronous read) (3)(8) 0 1.5 105+ 2.5 1.5 80 + 2.5 1.5 60+ 2.5 1.5 45- 2.5 ns clks 26 clock low to dsack0 and dsack1 asserted (synchronous read (3) 75 55 45 30 ns 27 start true to dsack0 and dsack1 asserted (synchronous read) (3)(8) 1.5 75+ 2.5 1.5 55+ 2.5 1.5 45+ 2.5 1.5 30- 2.5 ns clks table 7-3. ac electrical characteristics ? read and write cycles (1) (continued) v cc = 5.0 v dc 10%; gnd = 0 v dc; tc = -55c/+125c or tc = -40c/+85c (see figure 7-4 on page 16 , figure 7-5 on page 17 , figure 7-6 on page 18 ) n parameter 16.67 mhz 20 mhz 25 mhz 33.33 mhz unit minmaxminmaxminmaxminmax
14 0852b?hirel?06/07 ts68882 e2v semiconductors sas 2007 7.3 test conditions spec ific to the device 7.3.1 test load the applicable loading network shall be as defined in column ?test conditions? of table 4-1 , referring to the loading network number as shown in figure 7-2 . figure 7-2. test loads 7.3.2 ac electrical specification definitions the ac specifications presented consist of output delays, input setup and hold times, and signal skew times. all signals are specified relative to an appropriate edge of the clock input and, possibly, relative to one or more other signals. the measurement of the ac specifications is defined by the waveforms shown in figure 7-3 on page 15 . in order to test the parameters guaranteed inputs must be driven to the voltage levels specified in figure 7-3 . outputs are specified with minimum and/or maximum limits, as appropriate, and are measured as shown. inputs are specified with minimum and, an appropriate maximum setup and hold times, and are measured as shown. finally, the measurement for signal-to-signal specifications are also shown. note that the testing levels used to verify conforma nce to the ac specifications does not affect the guar- anteed dc operation of the device specifie d in the dc electrical characteristics.
15 0852b?hirel?06/07 e2v semiconductors sas 2007 ts68882 figure 7-3. drive levels and test poin ts for ac specifications legend a) maximum output delay specification. b) minimum output hold time. c) minimum input setup time specification. d) minimum input hold time specification. e) signal valid to signal valid specification (maximum or minimum). f) signal valid to signal invalid specification (maximum or minimum). notes: 1. this output timing is applicable to all parameters specified relative to the rising edge of the clock. 2. this output timing is applicable to all parameters specified relative to the falling edge of the clock. 3. this input timing is applicable to all parameters specified relative to the rising edge of the clock. 4. this input timing is applicable to all parameters specified relative to the falling edge of the clock. 5. this timing is applicable to all parameters specified relative to the assertion/negation of another signal.
16 0852b?hirel?06/07 ts68882 e2v semiconductors sas 2007 figure 7-4. asynchronous read cycle timing diagram note: start is actually a logical condition, but is shown as an active signal for clarity. the logical equation for this signal is: start = cs + as + (r/w ds ).
17 0852b?hirel?06/07 e2v semiconductors sas 2007 ts68882 figure 7-5. asynchronous write cycle timing diagram note: start is actually a logical condition, but is shown as an active signal for clarity. the logical equation for this signal is: start = cs + as + (r/w ds ).
18 0852b?hirel?06/07 ts68882 e2v semiconductors sas 2007 figure 7-6. synchronous read cycle timing diagram note: start is actually a logical condition, but is shown as an active signal for clarity. the logical equation for this signal is: start = cs + as + (r/w ds ). 7.4 additional information additional information shall not be for any inspection purposes. 7.4.1 capacitance (not for inspection purposes) symbol parameter test conditions min max unit c in input capacitance v in = 0 t amb = 25c 20 pf f = 1 mhz
19 0852b?hirel?06/07 e2v semiconductors sas 2007 ts68882 8. functional description 8.1 the co-processor concept the ts68882 functions as a co-processor in systems where the ts68020 or ts68030 is the main pro- cessor via the ts68000 co-processor interface. it func tions as a peripheral processor in systems where the main processor is the ts68000, ts68010. the ts68882 utilizes the ts68000 family co-processor interface to provide extension of the ts68020 /ts68030 registers and instruction set in a manner which is transparent to the programmer. the pro- grammer perceives the mpu/fpcp execution model as if both devices are implemented on one chip. a fundamental goal of the ts68000 family co-processor interface is to provide the programmer with an execution model based upon sequential instruction execution by the ts68020/ts68030 and the ts68882. for optimum performance, however, the co-p rocessor interface allows concurrent operations in the ts68882 with respect to the ts68020/ts68030 whenever possible. in order to simplify the pro- grammer?s model, the co-processor interface is designed to emulate, as closely as possible, non- concurrent operation between the ts68020/ts68030 and the ts68882. the ts68882 is s non-dma type co-processor which uses a subset of the general-purpose co-processor interface supported by the ts68020/ts68030. features of the interface implemented in the ts68882 are as follows: the main processor(s) and ts68882 comm unicate via standard ts68000 bus cycles the main processor(s) and ts68882 communications are not dependent upon the instruction sets or internal details of the individual devices (i.e., instruction pipes or caches, addressing modes) the main processor(s) and ts68882 may operate at different clock speeds ts68882 instructions utilize all addressing modes provid ed by the main processor; all effective addresses are calculated by the main processor at the request of the co-processor all data transfers are performed by the main processor at the request of the ts68882; thus memory management, bus errors, address errors, and bus arbitration function as if the ts68882 instructions are executed by the main processor overlapped (concurrent) instruction execution enhances throughput while maintaining the programmer?s model of sequential instruction execution co-processor detection of exceptions which require a trap to be taken are serviced by the main processor at the request of the ts68882 thus e xception processing functions as if the ts68882 instructions were executed by the main processor support of virtual memory/virtual machine systems is provided via the fsave and frestore instructions up to eight co-processors may reside in a system simultaneously: multiple co -processors of the same type are also allowed systems may use software emulation of the ts68882 without reassembling or relinking user software the ts68882 programming model is shown in figure 8-1 on page 20 through 15, and consists of the following: eight 80-bit floating-point data registers (fp0-fp7). these registers are analogous to the integer data registers (d0-d7) and are completely general-purpose (i.e., any instruction may use any register) a 32-bit control register that contains enable bits for each class of exceptions trap, and mode bits to set the user-selectable rounding and precision modes
20 0852b?hirel?06/07 ts68882 e2v semiconductors sas 2007 a 32-bit status register that contains floating-point condition codes, quotient bits, and exception status information a 32-bit instruction address register that contains the main processor memory address of the last floating-point instruction that was executed. this address is used in exception handling to locate the instruction that caused the exception the connection between the ts68020/ts68030 and th e ts68882 is a simple extension of the ts68000 bus interface. the ts68882 is connected as a co-processor to the ts68020/ts68030, and the selection of the ts68882 is based upon a chip select (cs), which is decoded from the ts68020/ts68030 function codes and address bus. figure 8-7 illustrates the ts6 8882/ts68020 or ts6 8030 configuration. figure 8-1. ts68882 programming model figure 8-2. exception status/enable byte
21 0852b?hirel?06/07 e2v semiconductors sas 2007 ts68882 figure 8-3. mode control byte figure 8-4. condition code byte figure 8-5. quotient byte figure 8-6. accrued exception byte prec rnd 76 54 3 2 10 0 rounding mode: 00 to nearest 01 toward zero 10 toward minus infinity 11 toward plus infinity rounding precision: 00 extended 01 single 10 double 11 (undefined reserved)
22 0852b?hirel?06/07 ts68882 e2v semiconductors sas 2007 figure 8-7. typical co-processo r configuration 8.2 bus interface unit all communications between the ts68020/ts68030 and the ts68882 occur via standard ts68000 family bus transfers. the ts68882 is designed to operate on 8-, 16-, or 32-bit data buses. the ts68882 contains a number of co-processor interface registers (cirs) which are addresses in the same manner as memory by the main processor. the ts68000 family co-processor interface is imple- mented via a protocol of reading and writing to thes e registers by the main processor. the ts68020 and ts68030 implements this general- purpose co-process or interface protocol in hardware and microcode. when the ts68020/ts68030 detects a typical ts68882 instruction, the mpu writes the instruction to the memory-mapped command cir, and reads the response cir. in this response, the biu encodes requests for any additional action required of the mpu on behalf of the ts68882. for example, the response may request that the mpu fetch an operand from the evaluated effective address and transfer the operand to the operated cir. once the mpu fulfills the co-processor request(s), it is free to fetch and execute subsequent instructions. a key concern in a co-proce ssor interface that allows concurrent instruction execution is synchronization during main processor and co-processor communication. if a subsequent instruction is written to the ts68882 before the ccu has passed the operands for the previous instructions to the ecu, the response instructs the ts68020/ts68030 to wait. thus, the choice of concurrent or nonconcurrent instruction execution is determined on an instruct ion-by-instruction basis by the co-processor. the only difference between a co-processor bus transfer and any other bus transfer is that the ts68020/ts68030 issues a function code to indicate the cpu address space during the cycle (the func- tion codes are generated by the ts68000 family processors to identify eight separate address spaces). thus, the memory-mapped co-processor interface registers do not infringe upon instruction or data address spaces. the ts68020/ts68030 places a co-processor id field from the co-processor instruction onto three of the upper address lines during co -processor accesses. this id, along with the cpu address space function code, is decoded to select one of eight co-processors in the system. since the co-processor interface protocol is based so lely on bus transfers, the protocol is easily emu- lated by software when the ts68882 is used as a peripheral with any processor capable of memory- mapped i/o over on ts68000 style bus.
23 0852b?hirel?06/07 e2v semiconductors sas 2007 ts68882 when used as a peripheral processor with the 8- bit ts68008 or the 16-bit ts68000, or ts68010, all ts68882 instructions are trapped by the main proces sor to an exception handler at execution time. thus, the software emulation of the processor interface protocol can be totally transparent to the user. the system can be quickly upgraded by replacing the main processor with a ts68020/ts68030 without changes to the user software. since the bus is asynchronous, the ts68882 need not run at the same clock speed as the main proces- sor. total system performance may therefore be customized. for example, a system requiring very fast floating-point arithmetic with relatively slow inte ger arithmetic can be designed with an inexpensive main processor and a fast ts68882. 8.3 co-processor interface the ts68000 family co-processor interface is an integral part of the ts68882 and ts68020/ts68030 designs, with the interface tasks shared between the two. the interface is fully compatible with all present and future ts68000 family products. tasks are partitioned such that the ts68020/ts68030 does not have to decode co-processor instructions and, the ts68882 does not have to duplicate main processor functions such as effective address evaluation. this partitioning provides an orthogonal extension of the instruction set by permitting ts68882 instruc- tions to utilize all ts68020/ts6803 0 addressing modes and to generate execution time exception traps. thus, from the programmer?s view, the cpu and co-processor appear to be integrated onto a single chip. while the execution of the majority of ts68882 instructions may be overlapped with the execution of ts68020/ts68030 instructions, concurrency is completely transparent to the programmer. the ts68020/ts68030 single-step and program flow (trace) modes are fully supported by the ts68882 and the ts68000 family co-processorco-processor interface. while the ts68000 family co-processor interface permits co-processors to be bus masters, the ts68882 is never a bus master. the ts68882 requests that the ts68020/ts68030 fetch all operands and store all results. in this manner, the ts68020/ts68030 32-bit data bus provides high speed transfer of floating-point operands and results while simplifying the design of the ts68882. since the co-processor interface is based solely upon bus cycles and the ts68882 is never a bus mas- ter, the ts68882 can be placed on either the logical or physical side of the system memory management unit. this provides a great deal of flexibility in the system design. the virtual machine architecture of the ts68000 family is supported by the co-processor interface and the ts68882 thro ugh the fsave and frestore instructions. if the ts68020/ts6 8030 detects a page fault and/or task time out, it can force the ts68882 to stop whatever operation is in process at any time (even in the middle of the execution of an instruction) and save the ts68882 internal state in memory. the size of the saved internal state of the ts68 882 is dependent u pon what the ccu and ecu are doing at the time that the fsave is executed. if the ts68882 is in the reset state when the fsave instruction is received, only one word of state is transferred to memory, which may be examined by the operating system to determine that the co-processor programmer?s model is empty. if the co-processor is idle when the save instruction is received, only a few words of internal state are transferred to memory. if the ts68882 is in the middle of performing a calculation, it may be necessary to save the entire internal state of the machine. instructions that can complete execution in less time than it would take to save the larger state in mid-instruction are allowed to complete execution and then save the idle state. thus the size of the saved internal state is kept to a minimum. the ab ility to utilize severa l internal state sizes greatly reduces the average context switching time.
24 0852b?hirel?06/07 ts68882 e2v semiconductors sas 2007 the frestore instruction permits reloading of an internal state that was saved earlier, and continue any operation that was previously suspended. restori ng of the reset internal state functions just like a hardware reset to the ts68882 in that defaults are re-established. note: though the ts68882 is instruction set compatible with the ts68881, the idle and busy state frames are both 32 bytes larger on the ts68882 than on the ts 68881. a unique format word is generated by the ts68882 so that system software can detect this difference. 8.4 operand data formats the ts68882 supports the following data formats: byte integer (b) word integer (w) long word integer (l) single precision real (s) double precision real (d) extended precision real (x) packed decimal string real (p) the capital letters contained in parenthesis denote su ffixes added to instructions in the assembly lan- guage source to specify the data format to be used. 8.5 integer data formats the three integer data formats (byte, word, and long word) are the standard data formats supported in the ts68000 family architecture. whenever an integer is used in a floating-point operation, the integer is automatically converted by the ts68882 to an ex tended precision floating-point number before being used. for example, to add an integer constant of five to the number contained in floating-point data reg- ister 3 (fp3), the following instruction can be used: fadd.w #5.fp3 the ability to effectively use integers in floating-point operations saves user memory since an integer representation of a number, if representable, is usually smaller than the equivalent floating-point representation. 8.6 floating-point data formats the floating-point data formats single precision (32-bits) and double precision (64-bits) are as defined by the ieee standard. these are the main floating-poi nt formats and should be used for most calculations involving real numbers. table 8-1 lists the exponent and mantissa size for single, double, and extended precision. the exponent is biased, and the mantis sa is in sign and magnitude form. since single and double precision require normalized numbers, the most si gnificant bit of the mantissa is implied as one and is not included, thus givi ng one extra bit of precision. table 8-1. exponent and mantissa sizes data format exponent bits mantissa bits bias single 8 23 (+1) 127 double 11 52 (+1) 1023 extended 15 64 16383
25 0852b?hirel?06/07 e2v semiconductors sas 2007 ts68882 the extended precision data format is also in conformance with the ieee standard, but the standard does not specify this format to the bit level as it does for single and double precision. the memory format on the ts68882 consists of 96 bits (three long words) . only 80 bits are actually used, the other 16 bits are for future expandability and for long-word alignment of floating-point data structures. extended for- mat has a 15-bit exponent, a 64-bit mantissa, and a 1-bit mantissa sign. extended precision numbers are intended for use as temporary variables, intermediate values, or in places where extra precision is needed. for example, a compiler might select extended precision arith- metic for evaluation of the right side of an equatio n with mixed sized data and then convert the answer to the data type on the left side of the equation. it is anticipated that extended precision data will not be stored in large arrays, due to the amount of memory required by each number. 8.7 packed decimal stri ng real data format the packed decimal string data format allows pack ed bcd strings to be input to and output from the ts68882. the strings consist of a 3-digit base 10 exponent and a 17-digit base 10 mantissa. both the exponent and mantissa have a separate sign bit. all di gits are packed bcd, such that an entire string fits in 96 bits (three long words). as is the case with all data formats, when packed bcd strings are input to the ts68882, the strings are automatically converted to extended precision re al values. this allows packed bcd numbers to be used as inputs to any operation. for example: fadd.p # - 6.023e + 24, fp5 bcd numbers can be output from the ts68882 in a format readily used for printing by a program gener- ated by a high-level language compiler. for example: fmove.p fp3.buffer (# -5) instructs the ts68882 to convert the floating-point data register 3 (fp3) contents into a packed bcd string with five digits to the right of the decimal point (fortran f format). 8.8 data format summary all data formats described above are supported orthog onally by all arithmetic and transcendental opera- tions, and by all appropriate ts68000 family addressi ng modes. for example, all of the following are legal instructions: on-chip calculations are performed to extended prec ision format, and the eight floating-point data regis- ters always contain extended precision values. al l data used in an operation is converted to extended precision by the ts68882 before the s pecific operation is performed, and all results are in extended pre- cision. this ensures accuracy without sacrificing performance. refer to figure 8-8 for a summary of the memory formats for the seven data formats supported by the ts68882. fadd.b # 3.fp0 fadd.w d2.fp3 fadd.l bigint.fp7 fadd.s # 3.14159.fp5 fadd.d (sp) + .fp6 fadd.x [(temp -ptr.a7)].fp3 fadd.p # 1.23e25.fp0
26 0852b?hirel?06/07 ts68882 e2v semiconductors sas 2007 figure 8-8. ts68882 data format summary 8.9 instruction set the ts68882 instruction set is organized into six major classes: 1. moves between the ts68882 and memory or the mpu (in and out) 2. move multiple registers (in and out) 3. monadic operations 4. dyadic operations 5. branch, set, or trap conditionally, and 6. miscellaneous 8.10 moves all moves from memory (or from an mpu data regist er) to the ts68882, cause data conversion from the source data format to the internal extended precision format. all moves from the ts68882 to memory (or to an mp u data register), cause da ta conversion from the internal extended precision format to the destination data format. byte integer 70 8 bits word integer long integer single real double real 15 0 0 31 0 0 0 0 62 51 16 bits sign of fraction 11-bit exp. 52-bit fraction sign of fraction 8-bit exp. 23-bit fraction 30 22 32 bits 94 80 63 15-bit exponent zero 64-bit mantissa sign of mantissa implicit binary point 2 bits, used only for = infinity or nans, zero otherwise sign of mantissa sign of exponent * unless a binary-to-decimal conversion overflow occurs extended real packed decimal real implicit decimal point 91 80 67 3-digit exp. zero* 17-digit mantissa
27 0852b?hirel?06/07 e2v semiconductors sas 2007 ts68882 note that data movement instructions perform arithmetic operations, since the result is always rounded to the precision selected in the fpcr mode control byte. the result is rounded using the selected round- ing mode, and is checked for overflow and underflow. the syntax for the move is: where: (ea) is a ts68000 family effective address operand an d (fmt) is the data format size. fpm and fpn are floating-point data registers. 8.11 move multiples the floating-point move multiple instructions on the ts68882 are much like the integer counterparts on the ts68000 family processors. any set of the fl oating-point registers fp0 through fp7 can be moved to or from memory with one instruction. these registers are always moved as 96-bit extended data with no conversion (hence no possibility of conversion errors). some move multiple examples are as follows: move multiples are useful during context switches and interrupts to save or restore the state of a pro- gram. these moves are also useful at the start and end of a procedur e to save and restore the calling routine?s register set. in order to reduce procedure call overhead, the list of registers to be saved or restored can be contained in a data register. this a llows run-time optimization by allowing a called rou- tine to save as few registers as possible. note that no rounding or overflow/underflow checking is performed by these operations. 8.12 monadic operations monadic operations have one operand. this operand may be in a floating-point data register, memory, or in an mpu data register. the result is always stored in a floating-point data register. for example, the syntax for square root is: the ts68882 monadic operations available are as follows: fmove.(fmt) (ea).fpn move to ts68882 fmove.(fmt) fpm.(ea) move from ts68882 fmove.x fpm.fpn move within ts68882 fmovem (ea), fp0-fp3/fp7 fmovem fp2/fp4/fp6,(ea) fsqrt.(fmt) (ea), fpn or, fsqrt.x fpm, fpn or, fsqrt.x fpn fabs absolute value facos arc cosine fasin arc sine fatan arc tangent fatanh hyperbolic arc tangent
28 0852b?hirel?06/07 ts68882 e2v semiconductors sas 2007 8.13 dyadic operations dyadic operations have two input operands. the first input operand comes from a floating-point data register, memory, or mpu data register. the second input operand comes from a floating-point data reg- ister. the destination is the same floating-point data register used for the second input. for example, the syntax for add is: the ts68882 dyadic operations available are as follows: fcos cosine fcosh hyperbolic cosine fetox e to the x power fetoxm1 e to the x power - 1 fgetexp get exponent fgetman get mantissa fint integer part fintrz integer part (truncated) flog10 log base 10 flog2 log base 2 flogn log base e flognp log base e of(x + 1) fneg negate fsin sine fsincos simultaneous sine and cosine fsinh hyperbolic sine fsqrt square root ftan tangent ftanh hyperbolic tangent ftentox 10 to the x power ftst test ftwotox 2 to the x power fabs absolute value facos arc cosine fadd.(fmt) (ea).fpnor, fadd.x fpm.fpn fadd add fcmp compare fdiv divide fmod modulo remainder
29 0852b?hirel?06/07 e2v semiconductors sas 2007 ts68882 8.14 branch, set, and trap-on condition the floating-point branch, set, and trap-on condition instructions implemented by the ts68882 are simi- lar to the equivalent integer instructions of the ts68000 family processors, except that more conditions exist due to the special values in ieee floating-poi nt arithmetic. when a condi tional instruction is exe- cuted, the ts68882 performs the necessary condition checking and tells the mpu whether the condition is true or false; the mpu then takes the appropriate action. since the ts68882 and ts68020/ts68030 are closely coupled, the floating-point branch oper ations executed by the pair are very fast. the ts68882 conditional operations are: where: cc is one of the 32 floating-point conditional test specifiers as shown in table 8-2 . rs fmul multiply frem ieee remainder fscale scale exponent fsgldiv single precision divide fsglmul single precision multiply fsub subtract fadd add fbcc branch fdbcc decrement and branch fscc set byte accord ing to condition ftrapcc trap-on condition (with an optional parameter) table 8-2. floating-point conditional test specifiers mnemonic definition note: the following conditional tests do not set the bsun bit in the status register exception byte under any circumstances. ffalse eq equal ogt ordered greater than oge ordered greater than or equal olt ordered less than ole ordered less than or equal ogl ordered greater or less than or ordered un unordered ueq unordered or equal ugt unordered or greater than
30 0852b?hirel?06/07 ts68882 e2v semiconductors sas 2007 8.15 miscellaneous instructions miscellaneous instructions include moves to and from the status, control, and instruction address regis- ters and a no operation function that can be used to ?flush? exceptions. also included are the virtual memory/machine fsave and frestore instructions that save and restore the internal state of the ts68882. uge unordered or greater or equal ult unordered or less than ule unordered or less or equal ne not equal ttrue note: the following conditional tests set the bsun bit in the status register exception byte if the nan condition code bit is s et when a conditional instruction is executed. sf signaling false seq signaling equal gt greater than ge greater than or equal lt less than le less than or equal gl greater or less than gle greater less or equal ngle not (greater, less or equal) ngl not (greater or less) nle not (less or equal) nlt not (less than) nge not (greater or equal) ngt not (greater than) sne signaling not equal st signaling true table 8-2. floating-point conditional test specifiers (continued) mnemonic definition fmove (ea),fpcr move to control register(s) fmove fpcr,(ea) move from control register(s) fnop no operation fsave (ea) virtual machine state save frestore (ea) virtual machine state restore
31 0852b?hirel?06/07 e2v semiconductors sas 2007 ts68882 8.16 addressing modes the ts68882 does not perform address calculations. this satisfies the criterion that a ts68000 family co-processor must not depend on ce rtain features or capabilities that may or may not be implemented by a given main processor. thus, when the ts68882 instructs the ts68020/ts68030 to transfer an oper- and via the co-processor interface, the mpu performs the addressing mode calculations requested in the instruction. in this case, the inst ruction is encoded specifically fo r the ts68020/ts68030, and the execu- tion of the ts68882 is not dependent on that encoding, but only on the value of the command word written to the ts68882 by the main processor. this interface is quite flexible and allows any addressi ng mode to be used with floating-point instructions. for the ts68000 family, these addressing modes include immediate, postincrement, predecrement, data or address register direct, and the indexed/indirect addressing modes of the ts68020/ts68030. some addressing modes are restricted for some instructions in keeping with the ts68000 family archi- tectural definitions (i.e., pc relative addressing is not allowed for a destination operand). the orthogonal instruction set of the ts68882, along with the flexible branches and addressing modes, allows a programmer writing assembly language code, or a compiler writer generating object or source code for the mpu/ts68882 device pair, to think of the ts68882 as though it is part of the mpu. there are no special restrictions imposed by the co-process or interface, and floating-point arithmetic is coded exactly like integer arithmetic. 8.17 address bus (a0 through a4) these active-high address line inputs are used by the main processor to select the co-processor inter- face register locations located in the cpu address space. these lines control the register selection as listed in table 8-3 . when the ts68882 is configured to operate over an 8-bit data bus, the a0 pin is used as an address sig- nal for byte accesses of the co-processor interface registers. when the ts68882 is configured to operate over a 16- or 32-bit system data bus, both the a0 and size pins are strapped high and/or low as listed in table 8-4 . table 8-3. co-processor interface register selection a4-a0 offset width type register 0000x s00 16 read response 0001x s02 16 write control 0010x s04 16 read save 0011x s06 16 r/w restore 0100x s08 16 - (reserved) 0101x s0a 16 write command 0110x s0c 16 - (reserved) 0111x s0e 16 write condition 100xx s10 32 r/w operand 1010x s14 16 read register select
32 0852b?hirel?06/07 ts68882 e2v semiconductors sas 2007 8.18 data bus (d0 through d31) this 32-bit, bi-directional, three-state bus serves as the general-purpose data path between the ts68020/ts68030 and the ts68882. regardless of whether the ts68882 is operated as a co-proces- sor or a peripheral processor, all inter-processor transfers of instruction information, operand data, status information, and requ ests for service occur as standard ts68000 bus cycles. the ts68882 will operate over an 8-, 16-, or 32-bit system data bus. depending upon the system data bus configuration, both the a0 and size pins are configured specifically for the applicable bus configura- tion. (refer to address bus (a 0 through a4) an d size (size for further details). 8.19 size (size ) this active-low input signal is used in conjunction with the a0 pin to configure the ts68882 for operation over an 8-, 16-, or 32-bit system data bus. when the ts68882 is configured to operate over a 16-or 32- bit system data bus, both the size and a0 pins are strapped high and/or low as listed in table 8-4 . 8.20 address strobe (as ) this active-low input signal indicates that there is a valid address on the address bus, and both the chip select (cs) and read/write (r/w signal lines are valid). 8.21 chip select (cs ) this active-low input signal enables the main processor access to the ts68882 co-processor interface registers. when operating the ts68882 as a peripheral processo r, the chip select decode is system dependent (i.e., like the chip select on any peripheral). the cs signal must be valid (either asserted or negated) when as is asserted. refer to chip select timing for further discussion of timing restric- tions for this signal. 8.22 read/write (r/w ) this input signal indicates the direction of a bus transaction (read/write) by the main processor. a logic high (1) indicates a read from the ts68882, and a logic low (0) indicates a write to the ts68882. the r/w signal must be valid when as is asserted. 1011x s16 16 - (reserved) 110xx s18 32 read instruction address 111xx s1c 32 r/w operand address table 8-4. system data bus size configuration a0 size data bus low 8-bit low high 16-bit high high 32-bit table 8-3. co-processor interface register selection a4-a0 offset width type register
33 0852b?hirel?06/07 e2v semiconductors sas 2007 ts68882 8.23 data strobe (ds ) this active-low input signal indicates that there is valid data on the data bus during a write bus cycle. 8.23.1 data transfer and size acknowledge (dsack0 , dsack1 ) these active-low, three-state output signals indicate the completion of a bus cycle to the main proces- sor. the ts68882 asserts both the dsack0 , and dsack1 signals upon assertion of cs . if the bus cycle is a main processor read, the ts68882 asserts dsack0 and dsack1 signals to indicate that the information on the data bus is valid. (b oth dsack signals may be asserted in advance of the valid data being placed on the bus). if the bus cycle is a main processor write to the ts68882, dsack0 and dsack1 are used to acknowledge acceptance of the data by the ts68882. the ts68882 also uses dsack0 and dsack1 signals to dynamically indicate to the ts68020/ts68030 the ?port? size (system data bus width) on a cycle- by-cycle basis. depending upon which of the two dsack pins are asserted in a given bus cyc le, the ts68020/ts68030 assumes data has been trans- ferred to/from an 8-, 16-, or 32-bit wide data port. table 8-5 lists the dsack assertions that are used by the ts68882 for the various bus cycles over the va rious bus cycles over the various system data bus configurations. table 8-5 indicates that all accesses over a 32-bit bus where a4 equals zero are to 16-bit registers. the ts68882 implements all 16-bit co-processor interface registers on data lines d16 - d13 (to eliminate the need for on-chip multiplexers); however, the ts68020/ts68030 expects 16-bit registers that are located in a 32-bit port at odd word addresses (a1 = 1) to be implemented on data lines d0-d15. for accesses to these registers when configured for 32-bit bus operation, the ts68882 generates dsack signals as listed in table 8-5 to inform the ts68020/ts68030 of valid data on d16 - d31 instead of d0-d15. an external holding resistor is required to maintain both dsack0 and dsack1 high between bus cycles. in order to reduce the signal rise time, the dsack0 and dsack1 lines are actively pulled up (negated) by the ts68882 following the rising edge of as or ds and both dsack lines are then three- stated (placed in the high-imped ance state) to avoid interf erence with the next bus cycle. 8.23.2 reset (reset) this active-low input signal causes the ts68882 to in itialize the floating-point data registers to non-sig- naling not-a-numbers (nans) and clears the floating -point control, status, and instruction address registers. when performing a power-up reset, external circuitry should keep the reset line asserted to a mini- mum of four clock cycles after v cc is within tolerance. th is assures correct init ialization of the ts68882 when power is applied. fo r compatibility with all ts68000 family devices, 100 milli seconds should be used as the minimum. table 8-5. dsack assertions data bus a4 dsack1 dsack2 comments 32-bit 1 l l valid data on d31-d0 32-bit 0 l h valid data on d31-d16 16-bit x l h valid data on d31-d16 or d15-d0 8-bit x h l valid data on d31-d24, d23-d16, d15-d8, d7-d0 all x h h insert wait states in current bus cycle
34 0852b?hirel?06/07 ts68882 e2v semiconductors sas 2007 when performing a reset of the ts68882 after v cc has been within tolerance for more than the initial power-up time, the reset line must have an asserted pulse width which is greater than two clock cycles. for compatibility with all ts68000 family devices, 10 cloc k cycles should be used as the minimum. 8.23.3 clock (clk) the ts68882 clock input is a ttl-compatible signal that is internally buffered for development of the internal clock signals. the clock input should be a c onstant frequency square wave with no stretching or shaping techniques required. the clock should not be gated off at any time and must conform to mini- mum and maximum period and pulse width times. 8.23.4 sense device (sense) this pin may be used optionally as an additional gnd pin, or as an indicator to external hardware that the ts68882 is present in the system. this signal is internally connected to the gnd of the die, but it is not necessary to connect it to the external ground for correct device operation. if a pullup resistor (which should be larger than 10 k ? ) is connected to this pin location, external hardware may sense the pres- ence of the ts688882 in a system. 8.23.5 power (v cc and gnd) these pins provide the supply volt age and system refe rence level for the internal circuitry of the ts68882. care should be taken to reduce the noise level on these pins with appropriate capacitance decoupling. 8.23.6 no connect (nc) one pin of the ts68882 package is designated as a no connect (nc). this pin position is reserved for future use, and should not be used for signal routing or connected to v cc or gnd. 8.23.7 interfacing methods ts68882/ts68020 or ts68030 interfacing the following paragraphs describe how to connect the ts68882 to a ts68020 or ts68030 for co-pro- cessor operation via an 8-, 16-, or 32-bit data bus. 8.23.8 32-bit data bus co-processor connection figure 8-9 illustrates the co-processor interface connection of a ts68882 to a ts68020/ts68030 via a 32-bit data bus. the ts68882 is configured to operate over a 32-bit data bus when both the a0 and size pins are connected to v cc . 8.23.9 16-bit data bus co-processor connection figure 8-10 illustrates the co-processor in terface connection of a ts68882 to a ts68020/t s68030 via a 16-bit data bus. the ts68882 is configured to operate over a 16-bit data bus when the size pin is con- nected to v cc , and the a0 pin is connected to gnd. the sixteen least significant data pins (d0-d15) must be connected to the sixteen most significant da ta pins (d16 - d31) when the ts68882 is configured to operate over a 16-bit data bus (i.e., connect d0 to d16, d1 to d17,... and d15 to d31). the dsack pins of the two devices are directly connected, although it is not necessary to connect the dsack0 pin since the ts68882 never asserts it in this configuration.
35 0852b?hirel?06/07 e2v semiconductors sas 2007 ts68882 8.23.10 8-bit data bus co-processor connection figure 8-11 illustrates the connecti on of a ts68882 to a ts 68020/ts68030 as a co-p rocessor over an 8- bit data bus. the ts68882 is configured to o perate over an 8-bit data bus when the size pin is con- nected to gnd. the twenty four least significant dat a pins (d0-d23) must be connected to eight most significant data pins (d24-d31) w hen the ts68882 is configured to operate over an 8-bit data bus (i.e., connect d0 to d8, d16 to d24; d1 to d9, d17, and d15;... and d7 to d15, d23 and d31). the dsack pins of the two devices are directly connected, although it is not necessary to connect the dsack1 pin since the ts68882 never asserts it in this configuration. ts68882/ts68000/ts68008/ts68010 interfacing the following paragraphs describe how to connect the ts68882 to a ts68000, ts68008, or ts68010 processor for operation as a peripheral via an 8- or 16-bit data bus. 8.23.11 16-bit data peripheral processor connection figure 8-12 illustrates the connection of a ts68882 to a ts 68000 or ts68010 as a peripheral processor over an 16-bit data bus. the ts68882 is configured to operate over an 16-bit data bus when the size pin is connected to v cc , and the a0 pin is connected to gnd. th e sixteen least significant data pins (d0- d15) must be connected to the sixteen most significant data pins (d16 - d31) when the ts68882 is con- figured to operate over an 16-bit data bus (i.e., connect d0 to d16, d1 to d17,... and d15 to d31). the dsack1 pin of the ts68882, is connected to the dtack pin of the main processor, and the dsack0 pin is not used. when connected as a peripheral processor, the ts68882 chip select (cs ) decode is system dependent. if the ts68000 is used as the main processor, the ts68882 cs must be decoded in the supervisor or user data spaces. however, if the ts68010 is used as the main processor, the moves instruction may be used to emulate any cpu space access that the ts68020/co-processorts68030 generates for co- processor communications. thus, the cs decode logic for such systems may be the same as in a ts68020/ts68030 systems, su ch that the ts68882 will not use any part of the data address spaces. figure 8-9. 32-bit data bus co-processor connection
36 0852b?hirel?06/07 ts68882 e2v semiconductors sas 2007 figure 8-10. 16-bit data bus co-processor connection figure 8-11. 8-bit data bus co-p rocessor connection gnd g n d
37 0852b?hirel?06/07 e2v semiconductors sas 2007 ts68882 figure 8-12. 16-bit data bus peripheral processor connection figure 8-13. 8-bit data bus peripheral processor connection
38 0852b?hirel?06/07 ts68882 e2v semiconductors sas 2007 8.23.12 8-bit data bus peripheral processor connection figure 8-13 illustrates the connection of a ts68882 to a ts 68008 as a peripheral pr ocessor over an 8-bit data bus. the ts68882 is configured to operate over an 8-bit data bus when the size pin is connected to gnd. the eight least significant data pins (d0-d7) must be connected to the twenty four most signifi- cant data pins (d8-d31) when the ts68882 is configured to operate over an 8-bit data bus (i.e., connect d0 to d8, d16 and d24; d1 to d9, d17, and d25;... and d7 to d 15, d 23, and d31). the dsack0 pin of the ts68882 is connected to the dtack pin of the ts68008, and the dsack1 pin is not used. when connected as a peripheral processor, the ts68882 chip select (cs ) decode is system dependent, and the cs must be decoded in the supervisor or user data spaces. 9. preparation for delivery 9.1 certificate of compliance e2v-grenoble offers a certificate of compliance with each shipment of parts, affirming the products are in compliance with mil-std-883 and guaranteeing the parameters are tested at extreme temperatures for the entire temperature range. 10. handling devices must be handled with certain precautions to avoid damage due to accumulation of static charge. input protection devices have been designed in the chip to minimize the effect of this static buildup. how- ever, the following handling practices are recommended: a) device should be handled on benches with conductive and grounded surface. b) ground test equipment, tools and operator. c) do not handle devices by the leads. d) store devices in conductive foam or carriers. e) avoid use of plastic, rubber, or silk. f) maintain relative humidity above 50%, if practical.
39 0852b?hirel?06/07 e2v semiconductors sas 2007 ts68882 11. package mechanical data figure 11-1. 68-lead cpga notes: 1. dimensions a and b are datums and t s datum surface. 2. positional tolerance for leads 168 places: 3. dimensioning and tolerancing per an5i y14 5m 1982. 4. controlling dimension: inch. ? 0,13 0,005 () t, a (5)|b (5)
40 0852b?hirel?06/07 ts68882 e2v semiconductors sas 2007 figure 11-2. 68-lead cqfp
41 0852b?hirel?06/07 e2v semiconductors sas 2007 ts68882 12. ordering information notes: 1. for availability of the different versions, contact your local e2v sales office. 2. the letter x in the part number designates a "prototype" pr oduct that has not been qualified by e2v. reliability of a pcx par t- number is not guaranteed and such part-number shall not be us ed in flight hardware. product changes may still occur while shipping prototypes. m: -55/+125?c v: -40/+85?c r: pin grid array 68 f: cqfp 68 1: hot solder dip (883c) (1) blank: gold ts xx y 68882 part identifier product code (1) ts(x) (2) 68882 temperature range (1) screening level hirel lead finish speed x x nnn (1) package 16: 16,67 mhz 20: 20 mhz 25: 25 mhz 33: 33,33 mhz blank: standard b/c = mil std 883 class b table 12-1. standard microcircuit dra wing (smd) cross-reference e2v orderable part-number standard microcircuit drawing (smd) number standard package lead-finish temperature frequency (mhz) ts68882mrb/c16 5962-8946301xc mil-prf- 38535 pga 68 gold -55c/+125c 16.67 ts68882mrb/c20 5962-8946302xc mil-prf- 38535 pga 68 gold -55c/+125c 20 ts68882mrb/c25 5962-8946303xc mil-prf- 38535 pga 68 gold -55c/+125c 25 ts68882mrb/c33 5962-8946304xc mil-prf- 38535 pga 68 gold -55c/+125c 33.33 ts68882mr1b/c16 5962-8946301xa mil-prf- 38535 pga 68 sn63pb37 -55c/+125c 16.67 ts68882mr1b/c20 5962-8946302xa mil-prf- 38535 pga 68 sn63pb37 -55c/+125c 20 ts68882mr1b/c25 5962-8946303xa mil-prf- 38535 pga 68 sn63pb37 -55c/+125c 25 ts68882mr1b/c33 5962-8946304xa mil-prf- 38535 pga 68 sn63pb37 -55c/+125c 33.33 ts68882mfb/c16 5962-8946301yc mil-prf- 38535 cqfp 68 gold -55c/+125c 16.67 ts68882mfb/c20 5962-8946302yc mil-prf- 38535 cqfp 68 gold -55c/+125c 20 ts68882mfb/c25 5962-8946303yc mil-prf- 38535 cqfp 68 gold -55c/+125c 25 ts68882mfb/c33 5962-8946304yc mil-prf- 38535 cqfp 68 gold -55c/+125c 33.33 ts68882mf1b/c16 5962-8946301ya mil-prf- 38535 cqfp 68 sn63pb37 -55c/+125c 16.67 ts68882mf1b/c20 5962-8946302ya mil-prf- 38535 cqfp 68 sn63pb37 -55c/+125c 20 ts68882mf1b/c25 5962-8946303ya mil-prf- 38535 cqfp 68 sn63pb37 -55c/+125c 25 ts68882mf1b/c33 5962-8946304ya mil-prf- 38535 cqfp 68 sn63pb37 -55c/+125c 33.33
42 0852b?hirel?06/07 ts68882 e2v semiconductors sas 2007 13. document revision history table 13-1 provides a revision history for this hardware specification. table 13-1. document revision history revision number date su bstantive change(s) b 06/2007 name change from atmel to e2v ordering information update a 04/2002 initial revision
whilst e2v has taken care to ensure the accuracy of the info rmation contained herein it accept s no responsibility for the conse quences of any use thereof and also reserves the right to change the specific ation of goods without notice. e2v accepts no liability beyond th at set out in its stan- dard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in acc ordance with informa- tion contained herein. how to reach us home page: www.e2v.com sales office: northern europe e2v ltd 106 waterhouse lane chelmsford essex cm1 2qu england tel: +44 (0)1245 493493 fax: +44 (0)1245 492492 e-mail: enquiries@e2v.com southern europe e2v sas 16 burospace f-91572 bivres cedex france tel: +33 (0) 16019 5500 fax: +33 (0) 16019 5529 e-mail: enquiries-fr@e2v.com germany and austria e2v gmbh industriestra?e 29 82194 gr?benzell germany tel: +49 (0) 8142 41057-0 fax: +49 (0) 8142 284547 e-mail: enquiries-de@e2v.com americas e2v inc. 4 westchester plaza elmsford ny 10523-1482 usa tel: +1 (914) 592 6050 or 1-800-342-5338, fax: +1 (914) 592-5148 e-mail: enquiries-na@e2v.com asia pacific e2v bank of china tower 30th floor office 7 1 garden rd central hong kong tel: +852 2251 8227/8/9 fax: +852 2251 8238 e-mail: enquiries-hk@e2v.com product contact: e2v avenue de rochepleine bp 123 - 38521 saint-egrve cedex france tel: +33 (0)4 76 58 30 00 hotline : std-hotline@e2v.com 0852b?hirel?06/07 e2v semiconductors sas 2007

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